The present invention relates to a PLL frequency synthesizer which matches the frequency of an output signal with a set frequency, and an optimal reset circuit for the PLL frequency synthesizer.
In recent years, PLL frequency synthesizers have been employed in mobile communication devices, such as cellular phones. A mobile communication device uses two frequency bands. The interval between each frequency is large. Thus, a voltage-controlled oscillator (VCO), which forms a PLL synthesizer, cannot handle frequency fluctuations. Accordingly, the PLL synthesizer is provided with a reset circuit for temporarily stopping the operation until the VCO stabilizes. Further, the PLL frequency synthesizer has a power-save function to reduce power consumption so that the battery of the mobile communication device lasts longer. The PLL frequency synthesizer provided with such functions must also be capable of immediately switching the frequency of an output signal to a desired one to improve performance of the mobile communication device.
FIG. 6 is a schematic block diagram showing a prior art PLL frequency synthesizer 10 including a reset circuit and provided with a power-save function.
A reference oscillator 11 provides a reference oscillation signal fosc to a reference counter 13 and an initial phase detector 14 via an input buffer 12. A comparison oscillation signal fin is divided by a comparison signal divider 15 and provided to a main counter 16 and the initial phase detector 14. The reference counter 13 divides the reference oscillation signal fosc based on a predetermined reference dividing ratio and provides a resulting divided signal, i.e., reference signal fr, to a phase comparator 17. The comparison signal divider 15 divides the comparison oscillation signal fin based on a predetermined dividing ratio and provides a resulting divided signal fpp to the main counter 16. The main counter 16 divides the divided signal fpp based on a predetermined comparison dividing ratio and provides a resulting divided signal, i.e., comparison signal fp, to the phase comparator 17.
The initial phase detector 14 receives the reference oscillation signal fosc and the divided signal fpp. If the reference oscillation signal fosc goes high during a predetermined period from when the divided signal fpp goes high, the initial phase detector 14 sends a command signal to the reference counter 13 and the main counter 16 to enable operation of the counters 13, 16. On the other hand, if the reference oscillation signal fosc remains low during the predetermined period from when the divided signal fpp goes high, the initial phase detector 14 provides the reference counter 13 and the main counter 16 with a command signal that inhibits operation of the counters 13, 16.
The phase comparator 17 receives the reference signal fr and the comparison signal fp to compare the rising edge of the reference signal fr with that of the comparison signal fp. The phase comparator 17 provides a pulse signal, which corresponds to the frequency difference and phase difference of the signals fr, fp, to a charge pump 18. A pull-up transistor or pull-down transistor of the charge pump 18 is activated based on the pulse signal from the phase comparator 17. A low-pass filter 19 connected to the charge pump 18 functions as a load applied to the charge pump 18. In the charge pump 18, activation of the pull-up transistor increases the output voltage, and activation of the pull-down transistor decreases the output voltage.
The low-pass filter 19 smoothes the output voltage of the charge pump 18 and sends the smoothed output voltage to a voltage control oscillator (VCO) 20. The VCO 20 generates a frequency output signal fvco corresponding to the output voltage of the low-pass filter 19. The output signal fvco is used as a transmission wave of the communication device. Further, the output signal fvco is provided to the comparison signal divider 15 as the comparison oscillation signal fin.
The PLL frequency synthesizer 10 locks the output signal fvco, which is used as a transmission wave, to a frequency corresponding to the reference dividing ratio of the reference counter 13 and the comparison dividing ratio of the main counter 16.
The PLL frequency synthesizer 10 also includes a reset circuit 51. The reset circuit 51 receives the reference signal fr from the reference counter 13, as a delayed clock CLK, and a frequency setting signal DIV. FIG. 7 is a block diagram showing the reset circuit 51.
The reset circuit 51 includes a delay circuit 52 and an exclusive NOR circuit 53. The delay circuit 52 has three D flip-flops (DFFs) 52a-52c. Each of the DFFs 52a-52c has a clock input terminal C, which receives the delayed clock CLK (reference signal fr) shown in FIG. 6. The first DFF 52a has a data input terminal D for receiving the frequency setting signal DIV and an output terminal Q connected to a data input terminal D of the second DFF 52b. The second DFF 52b has an output terminal Q connected to a data input terminal D of the third DFF 52c. 
The frequency setting signal DIV, which is provided by an external device, is a signal inverted between a high level and a low level each time the frequency of the output signal fvco generated by the PLL frequency synthesizer 10 changes.
More specifically, with reference to FIG. 8, subsequent to the rising of the frequency setting signal DIV and in response to a first pulse of the delayed clock CLK, the first DFF 52a holds the frequency setting signal DIV at the high level and outputs the frequency setting signal DIV (output signal SGA) from the output terminal Q. Then, when a second pulse of the delayed clock CLK is output, the second DFF 52b holds the output signal SGA, which is held and output by the first DFF 52a, at the high level and outputs the output signal SGA (output signal SGB) from the output terminal Q. Afterward, when a third pulse of the delayed clock CLK is output, the third DFF 52a holds the output signal SGB, which is held and output by the second DFF 52b, and outputs the output signal SGB (output signal SGC) from the output terminal Q.
Accordingly, the delay circuit 52, which includes the DFFs 52a-52c, acts as a shift register. If the level of the input frequency setting signal DIV shifts, the shift register shifts the level of the output frequency setting signal DIV (output signal SGC) when receiving three pulses of the delayed clock CLK subsequent to the level shift of the input frequency setting signal DIV.
The exclusive NOR circuit 53 receives the output signal SGC from the delay circuit 52 and the frequency setting signal DIV. If the level of the output signal SGC matches that of the frequency setting signal DIV, the exclusive NOR circuit 53 causes a reset signal, i.e., output signal OUT, to go high. If the level of the output signal SGC does not match that of the frequency setting signal DIV, the exclusive NOR circuit 53 causes the reset signal, i.e., output signal OUT, to go low. Therefore, when the level of the frequency setting signal DIV changes, the output signal OUT of the exclusive NOR circuit 53 is low from when the level changes to when three pulses of the delayed clock CLK are received.
The output signal OUT of the reset circuit 51 is provided to an internal circuit, i.e., the phase comparator 17. The phase comparator 17 is activated when the output signal OUT is high and deactivated when the output signal OUT is low. Thus, the phase comparator 17 stops operation (initialization) whenever the frequency setting signal DIV changes until three pulses of the delayed clock CLK have been received. That is, during the period from when the set frequency changes to when the VCO 20 stabilizes in response to the change, the reset circuit 51 temporarily stops operation (initialization) of the phase comparator 17 and deactivates the PLL frequency synthesizer 10.
Further, the PLL frequency synthesizer 10 receives a power-save signal PS, which is provided to the input buffer 12, the initial phase detector 14, the comparison signal divider 15, and the phase comparator 17. The power-save signal PS, which is provided by an external device, activates the PLL frequency synthesizer 10 when high and deactivates the PLL frequency synthesizer 10 when low.
The input buffer 12, the initial phase detector 14, the comparison signal divider 15, the main counter 16, and the phase comparator 17 are also deactivated when the power-save signal PS is low. In other words, when not in use, the PLL frequency synthesizer 10 is deactivated to reduce battery power consumption.
However, if the level of the frequency setting signal DIV shifts when in a power-save mode (the period during which the power-save signal PS is low), the PLL frequency synthesizer 10, which includes the reset circuit 51 experiences a problem, as described below.
FIG. 9 is a timing chart showing various signals when the power-save signal PS is shifted.
During the power-save mode (when the power-save signal PS is low), a shift in the level of the frequency setting signal DIV causes the output signal OUT of the reset circuit 51 to go low, which deactivates the phase comparator 17.
The PLL frequency synthesizer 10 is activated when the power-save mode is cancelled (when the power-save signal PS goes high). When the first DFF 52a of the reset circuit 51 receives the first pulse of the delayed clock CLK (reference signal fr) subsequent to cancellation of the power-save mode, the second and third DFFs 52b, 52c hold and do not shift the level of the frequency setting signal DIV. Thus, the output signal OUT of the reset circuit 51 remains low until the third DFF 52c holds the shifted frequency setting signal DIV. In other words, the activation of the PLL frequency synthesizer 10 is delayed. This delays the lockup operation performed by the PLL frequency synthesizer 10.
It is an object of the present invention to provide a PLL frequency synthesizer and a reset circuit that prevent a delayed lock-up operation even if the frequency setting signal is shifted during the power-save mode.
To achieve the above object, the present invention provides a reset circuit including a delay circuit for receiving a shift signal and generating an output signal by delaying the shift signal for a predetermined time. A determination circuit receives the shift signal and the output signal, determines whether the level of the shift signal matches the level of the output signal, and generates a non-matching signal for the predetermined time when the level of the shift signal is being shifted. The non-matching signal is provided as a reset signal to an internal circuit for the predetermined time. A control circuit receives a power-save signal, which deactivates the internal circuit. The control circuit provides the delay circuit with a control signal for matching the level of the output signal with the level of the shift signal when the power-save signal is cancelled.
Another aspect of the present invention provides a reset circuit for a PLL frequency synthesizer. The synthesizer includes a phase comparator that stops comparing the phase of a reference signal with the phase of a comparison signal for a predetermined time whenever the level of a frequency setting signal is shifted. The reset circuit includes a delay circuit for receiving the frequency setting signal and generating an output signal by delaying the frequency setting signal for a predetermined time. A determination circuit receives the frequency setting signal and the output signal, determines whether the level of the frequency setting signal matches a level of the output signal, and generates a reset signal for the predetermined time when the level of the frequency setting signal is shifted. The reset signal is provided to the phase comparator for the predetermined time. A control circuit receives a power-save signal and deactivates the phase comparator in response thereto. The control circuit provides the delay circuit with a control signal for matching the level of the output signal with the level of the frequency setting signal when the power-save signal is cancelled.
A further aspect of the present invention provides a reset circuit for a PLL frequency synthesizer. The synthesizer includes a phase comparator that stops comparing the phase of a reference signal with the phase of a comparison signal for a predetermined time whenever the level of a frequency setting signal is shifted. The reset circuit includes a delay circuit for receiving the frequency setting signal and generating a plurality of output signals, each having a different delay time, based on the frequency setting signal. A time adjustment circuit selects and outputs one of the plurality of output signals. A determination circuit receives the frequency setting signal and the output signal selected by the time adjustment circuit, determines whether the level of the frequency setting signal matches the level of the selected output signal, and generates a reset signal for the predetermined time when the level of the frequency setting signal is shifted. The reset signal is provided to the phase comparator for the predetermined time. A control circuit receives a power-save signal, which deactivates the phase comparator. The control circuit provides the delay circuit with a control signal for matching the level of the selected output signal with the level of the frequency setting signal when the power-save signal is cancelled.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.